1. Field of the Invention
The invention relates to a boost circuit. Particularly, the invention relates to a word line boost circuit.
2. Description of Related Art
FIG. 1 is a bias schematic diagram of a conventional memory unit in reading. Referring to FIG. 1, the conventional memory unit 100 includes a select transistor MS1 and a memory cell MC1. During the read operation, a word line driver (not shown) provides a selection voltage of −1.2V to a word line WL1, and a voltage of 1.8V is applied on a source line SL1, so as to turn on the select transistor MS1. Moreover, voltages of 1.8V and 0.3V are respectively applied on a control line CL1 and a bit line BL1. In this way, a sensing circuit in a memory device can determine a state of the memory cell MC1 according to a magnitude of a sensing current 101.
Moreover, before the read operation, the word line driver provides an operation voltage of 1.8V to the word line WL1. In other words, during the read operation, the word line driver has to provide the selection voltage (−1.2V) lower than the operation voltage (1.8V) to the word line WL1. Therefore, in an actual application, the memory device includes a word line boost circuit, and the word line boost circuit generates the selection voltage in a manner of negative boosting. Generally, the conventional word line boost circuit detects variation of a column-row address signal through an address transfer detector. When the column-row address signal is varied, a booster in the conventional word line boost circuit generates a boost voltage of −1.2V, so that the conventional word line boost circuit can generate the selection voltage by using the boost voltage.
For example, FIG. 2 is a signal waveform diagram of the conventional word line boost circuit, in which a column-row address signal PA1 has 12 bits, and only the front 4 bits PAY<0>-PAY<3> and a twelfth bit PAX<11> of the column-row address signal PA1 are shown in FIG. 2. Moreover, the front 5 bits of the column-row address signal PA1 are used to represent a bit line address (BL address), and the remained 7 bits are used to represent a word line address (WL address). Moreover, KICKB represents a boost clock signal formed by boost pulses which determines the timing of boost operation, VBB represents an output signal of the booster in the conventional word line boost circuit, ENBOOST represents a signal formed by enable pulses which determines the timing of switching operation, and ZWL represents a signal received by the word line WL1.
As shown in FIG. 2, during a period between time points t21 and t22, the row address of the selected memory unit is not varied and selects the same word line WL1. However, although the row address of the selected memory unit is not varied, as the column address of the memory unit is varied, the conventional word line boost circuit continually performs boost operations according to boost pulses P21-P25 and continually generates enable pulses in the signal ENBOOST, so as to continually switch the output signal VBB from 0V to −1.2V. Therefore, in the actual operation, power consumption of the conventional word line boost circuit is very high.